DESIGN UNIVERSAL GATE NAND & NOR USING VHDL CODE

AIM:- To Design universal gates  NAND&NOR.
APPARATUS:- XILINX software, ISIM simulator.
THEORY:-
NAND gate:- The Logic NAND Gate is a combination of the digital logic AND gate with that of an inverter or NOT gate connected together in series. The NAND (Not – AND) gate has an output that is normally at logic level “1” and only goes “LOW” to logic level “0” when ALL of its inputs are at logic level “1”. The Logic NAND Gate is the reverse or “Complementary” form of the AND gate.
Logic NAND Gate Equivalence

NOR gate:-
The Logic NOR Gate or Inclusive-NOR gate is a combination of the digital logic OR gate with that of an inverter or NOT gate connected together in series. The NOR (Not – OR) gate has an output that is normally at logic level “1” and only goes “LOW” to logic level “0” when ANY of its inputs are at logic level “1”. The Logic NOR Gate is the reverse or “Complementary” form of the OR gate.

Program for NAND gate:-
entity nand_g is
    Port ( X : in  STD_LOGIC;
           Y : in  STD_LOGIC;
           F : out  STD_LOGIC);
end nand_g;
architecture Behavioral of nand_g is
begin
            process(X,Y)
            begin
             if((X='1') and (Y='1')) then
                        F<='0';
             else
                        F<='1';
             end if;
            end process;
end Behavioral;