DESIGN BASIC GATES AND, OR, NOT BY USING VHDL CODE

AIM:- To DESIGN BASIC GATES AND, OR, NOT.
APPARATUS:- XILINX software, ISIM simulator.
THEORY:-
AND gate:- The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.  A dot (.) is used to show the AND operation i.e. A.B.  Bear in mind that this dot is sometimes omitted i.e. AB
             

OR gate: The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high.  A plus (+) is used to show the OR operation.
           

NOT gate: The NOT gate is an electronic circuit that produces an inverted version of the input at its output.  It is also known as an inverter.  If the input variable is A, the inverted output is known as NOT A.
             

Program:-
entity BASIC_G is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           D : out  STD_LOGIC;
           E : out  STD_LOGIC;
           F : out  STD_LOGIC);
end BASIC_G;
architecture Behavioral of BASIC_G is

begin
PROCESS(A,B)
begin
D<=A AND B;
E<=A OR B;
F<= NOT A;
END PROCESS;
end Behavioral;