Design or Program for XOR gate in data flow type using VHDL Code

library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1 : in std_logic;
ip2 : in std_logic;
op1 : out std_logic
);
end my_exor;

architecture my_exor_beh of my_exor is
begin
op1 <= (ip1 and (not ip2)) or
(ip2 and (not ip1));
end my_exor_beh;