Design Half adder and Full adder by using VHDL Code

AIM:- To Design Half adder and Full adder.
APPARATUS:- XILINX software, ISIM simulator.
THEORY:-
Half adder:- The half adder is an example of a simple, functional digital circuit built from two logic gates.  The half adder adds to one-bit binary numbers (AB).  The output is the sum of the two bits (S) and the carry (C).
Note the same two inputs are directed to two different gates.  The inputs to the XOR gate are also the inputs to the AND gate.  The input "wires" to the XOR gate are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate, the A input to the AND gate receives the same voltage.
Select an input combination from the pull-down selector and view the resulting output.
Circuit Diagram and Truth Table of half adder:-

       

Full adder:- The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1).   The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers.  The carry input for the full-adder circuit is from the carry output from the circuit "above" itself in the cascade.  The carry output from the full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see the full adder is simply two half adders joined by an OR.

Circuit Digram and Truth Table of Full adder:-

Program for Half adder:-
entity andgate is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : out  STD_LOGIC);
end andgate;
architecture Behavioral of andgate is
begin
c <= a and b;
end Behavioral;

entity xorgate is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           S : out  STD_LOGIC);
end xorgate;
architecture Behavioral of xorgate is
begin
s<= a xor b;
end Behavioral;

entity halfadder is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           S : out  STD_LOGIC;
           C : out  STD_LOGIC);
end halfadder;
architecture Behavioral of halfadder is

component xorgate is
port (a,b: in std_logic; s: out std_logic);
end component;
component andgate is
port (a,b: in std_logic; c: out std_logic);
end component;
begin
X1: xorgate port map (a,b,s);
A1: andgate port map (a,b,c);
end Behavioral;

Program for Full Adder using above half adder:
Program for Full adder:-
entity fulladder is
    Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           Cin : in  STD_LOGIC;
           S : out  STD_LOGIC;
           Cout : out  STD_LOGIC);
end fulladder;
architecture Behavioral of fulladder is
component halfAdder is
port( A, B  : in std_logic;
S, C : out std_logic);
end component;
component orGate is
port( A, B : in std_logic;
S : out std_logic);
end component;
signal x,y,z: std_logic;
begin
h1: halfadder port map (a,b,x,y);
h2:halfadder port map (y,cin,z,s);
o1: orgate port map(x,z,cout);
end Behavioral;


Output of Half adder:

Output of Full adder: