Design or Program for XOR gate in data flow (signal) type using VHDL Code

beh; Internal connections are made using signals.
Signals are defined inside the architecture.

library IEEE;
use IEEE.std_logic_1164.all;
entity my_exor is
port (ip1 : in std_logic;
ip2 : in std_logic;
op1 : out std_logic
);
end my_exor;
architecture exor_w_sig of my_exor is
signal temp1, temp2 : std_logic;
begin
temp1 <= ip1 and (not ip2);
temp2 <= ip2 and (not ip1);
op1 <= temp1 or temp2;
end exor_w_sig;